1. Field of the Invention
The present invention relates generally to analog-to-digital converters, but more particularly to a propagatory analog-to-digital converter which uses peristaltic charge-coupled-devices in the analog delay line portion thereof.
2. Description of the Prior Art
There has always been and will continue to be a need for ultra high speed analog-to-digital converters (hereinafter ADC's). In many technological areas, the speed of conversion and/or the resolution of ADC's have been major factors that have limited otherwise achievable overall system performance. For example, a prerequisite for obtaining enhanced radar performance is the inclusion of ultra high speed and high resolution ADC's. Consequently, there is a need in the prior art to configure an ADC having the foregoing qualities.
Many types of ADC's are available in the prior art. Generally speaking, they are classified as to type by the manner in which conversion takes place. The types that have been most successful are those that have been adapted to perform particular functions. An example is the dual-slope integrating ADC which is used almost exclusively in the digital voltmeter industry. The process of integrating up, then down, tends to cancel nonlinearities and other errors introduced by the process.
The successive approximation ADC is the most popular by far of the many available types. It combines resolution, conversion speed, and cost in a way that satisfies many applications. Those applications requiring moderately high conversion rates would normally use a successive approximation ADC. It is lower in cost, more reliable in operation and consumes less power than other types with similar conversion rates.
Hence, there is a need in the prior art to configure an improved ADC that is not only, inter alia, ultra high in conversion rate, but flexible in its application to many fields of use like the foregoing, and fields of use such as telemetry, telecommunications, digital filtering and processing, spectrum analysis and other related fields of use.
One approach to ultra high speed analog-to-digital conversion is the n-bit propagatory ADC. An n-bit propagation ADC has n stages, each of which performs a simultaneous one-bit analog-to-digital conversion. The n stages are not identical, increasing in complexity with distance from the input. The reason for this is that each stage of the analog-to-digital conversion system has individual storage and digital-to-analog conversion, with the number of bits increasing by one from the i-1 to the i.sup.th stage. Its parallel binary output is an n-bit representation of the analog input signal that was present at the input n clock periods before.
While the foregoing approach to ultra high speed propagatory ADC's are known in the prior art, as far as is known, the implementation thereof has been unsuccessful due to the use of tapped inductive type delay lines as the analog delay line and other discrete components. Consequently, the systems in the prior art were bulky, and unreliable. Moreover, a basic problem was maintaining the timing and the fidelity of the analog signal while it progressed down a large and bulky analog delay line.
Thus, there is a need in the prior art to configure an ADC based on the concept of propagation and to use peristaltic charge-coupled-devices (hereinafter, PCCD's) in the analog delay line portion thereof thereby maintaining and in the general case increasing the conversion speed, and decreasing the size.
There is a related need in the prior art to the above need to use hybrid circuitry and/or very large scale integration (VLSI) techniques for the fabrication of the propagatory ADC according to the present invention.
As for as can be determined, no prior art n-bit propagatory ADC incorporates all of the improvements, features and advantages of the present invention.